1. Field of the Invention
The present invention relates generally to dynamic random access memories (DRAMS), and more particularly to a method for forming a storage node which utilizes a reduced number of polyfills and chemical-mechanical polishes that provides a smooth transition between the node dielectric and the collar oxide of the storage node.
2. Description of the Prior Art
Deep trench-based storage devices are commonly used in DRAM cells. Such devices are typically etched 4-8 um deep into the silicon substrate. The process used for forming the deep trench differs between 4 Mb, 16 Mb, 64 Mb, 256 Mb, and 1 GB DRAM cells, however, there are a given number of process steps that are common to each generation of DRAM cell. The commonly performed deep trench processing steps, which constitute a large portion of the cost of making each of these trench-based DRAM cells, are as follows: the deposition of a node dielectric by low pressure chemical vapor deposition (LPCVD) of SiN, the reoxidation of the node dielectric, the deposition of a first polysilicon fill rising LPCVD, the chemical mechanical polish of the first polysilicon fill, the etching of a first recess in the first polysilicon fill using reactive ion etching (RIE), the deposition of a collar oxide, the etching of the collar oxide using RIE, the deposition of a second polysilicon fill using LPCVD, and the chemical mechanical polish the second polysilicon fill.
In the 256 Mb DRAM deep trench process, the connection between the storage trench and its associated array transistor is provided by a third polysilicon fill that is etched 50 nm below the silicon surface. This processing step is commonly referred to as the "buried strap formation". The buried strap process complicates the deep trench process and makes the deep trench process significantly more costly.
Another problem associated with the 256 Mb DRAM cell process relates to the vulnerability of the top portion of the SiN node dielectric. In current deep trench processing, the node dielectric is etched off the sidewalls of the trench. The depth of the node dielectric etch is determined by the first deep trench recess formed in the first polysilicon fill. The top portion of the node dielectric is susceptible to damage by the deep trench recess, the node dielectric etch, and collar oxide etch processes. The node dielectric thickness presently used is 6 nm, however, the final targeted thickness is even thinner or approximately 5 nm. In large deep trench test macros (224 Mb deep trenches), it has been found that shorting between the deep trenches is more prevalent when the first deep trench recess and, the node and collar oxide etch process are used. Conversely, when these processes are not used, the frequency of shorting between the deep trenches is negligible.
The shorting that occurs between the trenches originates at exposed areas of the deep trench sidewall which are at the top of the node dielectric. An exposed portion of the deep trench sidewall will eventually leave the substrate in contact with the polysilicon fill thus, causing shorts. As the node dielectric is further scaled down to 5 nm, these "extrinsic" fails will become even more ubiquitous.
It is, therefore, an object of the present invention to provide a simplified method for forming a storage node in a deep trench process which reduces the number of polysilicon fills and chemical-mechanical polishes and also provides a smooth transition between the node dielectric and the collar oxide.